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Dustin Kendig, VP of Engineering, Microsanj
  

Thermal Imaging of Electronic and Optoelectronic Devices (February 14, 2012)

Thermal characterization on a micron scale is an emerging challenge for electronic and optoelectronic device development. Junction temperatures are no longer a meaningful measurement since multiple hotspots exist on a die. Space limitations on the die preclude the use of embedded thermal sensors for thermal characterization. Full field thermal imaging technology on the other hand, provides rich information to enable visual detection of irregularities beyond what can be detected with spot temperature measurements.

Thermoreflectance imaging is a method for quickly obtaining a thermal image on micron-scale devices with excellent spatial and temperature resolution. The uniqueness and benefits of the thermoreflectance technique are introduced with the NT200-Series Thermoreflectance Image Analyzer and the SanjVIEWTMsoftware package.  Examples include the thermal imaging of a CMOS thermal test chip from TEA Inc., in a wire-bond package and a flip-chip package (with through-silicon imaging). The transient response of the built-in heaters provides a footprint of the chip’s thermal profile. These thermoreflectance images are compared with conventional infrared (IR) images on the same samples. The example further explores other types of devices, such as LEDs, micro coolers, micro vias, and solar cells. The thermal images help to identify potential defects that affect reliability in devices with submicron features.

  

Dustin Kendig graduated Cum Laude from the University of California Santa Cruz with a B.S. in Electrical Engineering in 2009. His university research focused on high resolution thermal imaging and the characterization of defects in solar cells. He is the author or co-author in more than 10 journal and conference papers. He was the winner of the Huffman Prize, Dean’s Award, and Chancellor’s Award in 2009 at UCSC. Dustin is a member of the Engineering Honor Society Tau Beta Pi.

 

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David Nelson, Principal Consultant, Nelson Acoustics
  

Forecasting Noise Emission and Power Consumption of Fan-cooled Devices (January 10, 2012)

Acoustic noise emission requirements are tightening and power densities are generally increasing. While seeking to provide adequate cooling airflow, thermal engineers need to know the consequences of various design choices such as fan type, diameter, number, flow-path back-pressure and inlet conditions. Noise Acoustics uses an empirical method based on general design parameters to quickly evaluate various configurations and to help steer towards an optimal solution in which all requirements are met.

  

David Nelson has thirty years of experience in fan noise, product design, sound quality, and many other diverse aspects of acoustics. He is Principal Consultant of Nelson Acoustics, located in the Austin, Texas area. He is a recognized expert in the area of low-noise cooling fan implementation, and as a consultant enjoys distilling otherwise obscure and complex science into clear, practical guidance. He is Board Certified by the Institute of Noise Control Engineering.

He is a recognized expert in the area of low-noise cooling fan implementation, and as a consultant enjoys distilling otherwise obscure and complex science into clear, practical guidance. He is Board Certified by the Institute of Noise Control Engineering.

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Dr. Greg Xiong, Research Scientist, Senior Staff Engineer at NetApp Inc
  

Thermocouple Attachment Using Epoxy in Electronic System Thermal Measurements (November 15, 2011)

Thermocouples are widely used in electronics thermal measurement but the often-neglected question is how good the results are? In this presentation we defined two parameters to analyze the error introduced by thermocouple attachment. A total of eight parameters that could affect data accuracy were investigated. The error was found to be 25 ~ 40% in some cases, however, a number of means can be taken to minimize it. Thermal engineers can use findings from this study to achieve their best practice.

  

Dr. Greg Xiong is a senior staff engineer at NetApp Inc., where he has been responsible for the company's thermal research and development activities since year 2000. Prior to NetApp, he had worked at Rockwell Science Center, and spent a number of years at various US universities with research projects funded by the US NAVY, AFOSR and NASA.

Dr. Xiong is the author of more than 20 external publications in peer-reviewed international conferences and journals, 2 US patents, and over 200 internal technical reports. Dr. Xiong holds a Ph.D. degree from Tsinghua University, Beijng, and B.E. degree from Shanghai Jiaotong University.

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Dr. Niru Kumari, Research Scientist, Sustainable Ecosystem Research Group at HP Labs
  

Holistic Multiscale Modeling of Data Center Energy Costs (October 11, 2011)

The rising energy consumption in the data centers is a topic of growing concern due to related cost and environmental impacts. The talk will review an end to end physical model that can be used to design and manage dense data centers and determine the cost of operating a data center. The model is used to explore impact of various management choices such as elevated data center air temperature and aisle containment on data center energy costs.

 

Dr. Niru Kumari is a research scientist in Sustainable Ecosystem Research Group at HP Labs in Palo Alto, CA. Her research is focused on energy and thermal management of sustainable data centers. She holds a MS and PhD from Purdue University in Mechanical Engineering where her research involved nanotechnology, superhydrophobic surfaces, electrowetting and electronics cooling.

 

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Thomas S. Tarter, Package Science Services LLC
  

Hot Spots: Methods for Detection and Analysis (August 9, 2011)

Thermal problems are common in today’s world of high performance devices. Chips are getting smaller and power density is going up. Due to these common phenomena and the ever increasing need for smaller, faster devices many problems that could be overlooked in the past are now becoming production roadblocks. The primary focus of this talk is how to find problems in packages related to heat transfer and cooling. These problems are not bulk issues or catastrophic material failures which are typically moderately simple to identify, but rather small failures or process defects which may not be easily identified. This talk will discuss failure analysis methods to find defects such as voids in die attach or under fill layers, package structural problems and other issues that impede heat flow in packaged IC’s. I will discuss analytical methods such as acoustic microscopy, x-ray and test techniques for design and assembly verification in the development and production modes and what reliability tests can be used to accelerate the defect propagation or failure mode exacerbation. The talk will detail the approaches for analysis, the limits of the equipment and methodology and some ideas on how to fix the problem once it is identified.

  

Thomas S. Tarter is an expert on thermal management, thermal and electrical characterization, and design of microelectronic and optoelectronic packaging structures. He spent 17 years at AMD in package characterization and was a Senior Member of the Technical Staff. Subsequently he was Director of BGA Package Engineering and Design at Advanced Interconnect Technology, and Principal Engineer for thermal management, temperature control and package development at NeoPhotonics Corporation, Inc.

In 2009, Tom started Package Science Services LLC, to serve the high-tech community with electronic packaging expertise in design, analysis, and characterization (electrical, thermal, reliability) and support all phases of IC, solar cell, LED and other chip packaging from concept to hand off to mass manufacturing. Tom has published 30 papers, holds 5 patents, and has presented numerous short courses and lectures. He chaired the JEDEC JC15.1 task group on thermal standards for five years, was general chair of SEMI-THERM, Technical Chair for five years, and serves on the SEMI-THERM executive committee to date. Tom is a senior member of IEEE and was chair of the IEEE Santa Clara Valley Chapter of CPMT for two years. Society affiliations include, IEEE, LEOS, Santa Clara Valley Nanotechnology Council, MEPTEC, IMAPS, and SPIE.

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Nate Hanlon, Applications Engineer, Mechanical Analysis Division, Mentor Graphics
  

LED Based System Thermal Design Methods (June 14, 2011)

Thermal management is said to be the most critical aspect of LED system design. Elevated operating temperatures can decrease an LED's luminous efficacy, cause color shifts, and reduce the device's lumen maintenance. Thermal management of LED systems require increased consideration due to the operating temperature's direct influence on LED optical performance. The operating temperature also directly effects the amount of heat that needs to be efficiently rejected by the thermal design.

In this presentation we will discuss in more detail the unique challenges related to developing a LED based system thermal design. We will also cover the role of measurement and analytical methods during the various phases of the design.

  

Nate Hanlon is an Applications Engineer working in the Mechanical Analysis Division of Mentor Graphics, where he works with Mentor Graphics CFD tools to perform thermal and airflow analysis on a wide range of engineering problems including electronic systems, data centers and clean rooms. Nate is also the Mechanical Lead at Mentor Graphics' San Jose based Thermal Test Facility.

Nate achieved his Mechanical Engineering Degree from San Jose State University in May 2007. Nate has spent the last 5 years working for Mentor Graphics Corporation, Mechanical Analysis Division (formerly Flomerics Ltd) specializing in the application of CFD to the design of the built environment and electronic equipment. Prior to this he worked as a lab technician for Comair Rotron in San Diego CA.

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Dr. Robert J. Moffat, Stanford University
  

Uncertainty Analysis: Living with Measurement Error and Uncertainty (May 10, 2011)

Uncertainty analysis has moved into prime time in the last 20 years. People at every level of every company that makes and sells product worry about measurement error and uncertainty – and they should! After all, customers will complain about your product if it doesn’t meet specs when they test it. It is important to be able to talk sensibly with them about the test measurement and uncertainty in order to support your claims.

Fortunately, uncertainty analysis is NOT the exclusive domain of statisticians – it fits well into the lives of test engineers and is a great help in developing good test methods. Uncertainty analysis, as a practical engineering tool, is done with a simple spreadsheet. It is 99% judgment (What are the input uncertainties?) and 1% statistics (the RSS combination).

We will take a quick look at the sources and types of error in test measurements, and illustrate the present approach with some examples from electronics cooling and gas turbine testing. Everything discussed is consistent with PTC 19.1 and its derivatives. All of this in 45 minutes!

  

Dr. Robert J. Moffat is a Professor of Mechanical Engineering (Emeritus) at Stanford University and President of Moffat Thermosciences, Inc.   Prof. Moffat started his professional career in the Gas Turbine Laboratory at General Motors Research Laboratories upon graduation from the University of Michigan.   After 10 years at GMR, he left for graduate studies at Stanford University, completing the requirements for Master of Science and Ph.D. in Mechanical Engineering. He was appointed Acting Associate Professor, 1966, Associate Professor, 1967, and Professor of Mechanical Engineering, 1972. He served as the Director of the Thermosciences Industrial Affiliates Program from 1967 to 1986 and as Chairman of the Thermosciences Division from 1973 to 1986.

 

His research efforts have involved three areas: convective heat transfer in engineering systems, experimental methods in heat transfer and fluid mechanics, and biomedical thermal issues.
Professor Moffat was an invited lecturer for 40 consecutive years in the Measurement Engineering Series (originally through Arizona State University), for more than 20 years in the Instrument Society of America Test Measurements Division Professional Development Program and, for ten years, in the ASME Professional Development program.

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Dr. Younes Shabany, Director of Thermal Engineering & Design and Thermal Architect, Flextronics International
  

New Thermal Management Drivers; What Roles Global EMS Companies Play? (April 12, 2011)

Electronic devices and systems have gone through aggressive miniaturization and extensive performance improvement in the last two decades. Despite the significant progress in material engineering and power management techniques, this has been accomplished by an increase in their power consumption and operating temperature. The effects of high temperature, and temperature variation, on accelerating electrical and mechanical failures and reducing reliability of electronic devices have been well known. That is why thermal management has been a critical design element for the realization of high-power density electronic systems. However, in recent years, other drivers of thermal management have become as important as failure prevention and reliability improvement. Some of these new thermal management drivers are power saving or energy efficiency, acoustic noise reduction, consumer comfort, and cost reduction. These new thermal management drivers, their relative importance in different markets, and the role that global Electronic Manufacturing Services companies play will be discussed in this talk.

  

Younes Shabany received his BS in mechanical engineering from Sharif University of Technology in Tehran, Iran, in 1991. He then went to Vancouver, Canada where he obtained his MS in mechanical engineering from the University of British Columbia in 1994. He came to the United States and received a Ph.D in mechanical engineering with a minor in aeronautics and astronautics from Stanford University, California, in 1999. Dr. Shabany has over 18 years of experience in thermal-fluid engineering. He is currently Director of Thermal Engineering & Design and Thermal Architect in Advanced Technology Group at Flextronics International USA, Milpitas, California. In this position, he has been leading thermal design activities in Flextronics’ worldwide design centers on a variety of infrastructure, computing, consumer, automobile, medical, and power electronic products.

 

Before Flextronics, he worked for Applied Thermal Technologies, Santa Clara, California, where he was the director for two years. While at Applied Thermal Technologies, he worked with over 60 companies and designed thermal solutions for about as many pieces of electronic equipment including telecom and networking equipment, desktop and laptop computers, biomedical equipment, and consumer products. Dr. Shabany has also been a lecturer at San Jose State University, California, since the summer of 2001. He has taught undergraduate and graduate courses in heat transfer and advanced mathematical analysis including his most favorite course, Heat Transfer in Electronics. He has also advised graduate students on their projects and theses.

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Ernie Thurlow, Thermal/Mechanical Design Engineer, Volterra Semiconductors
  

Thermal Design Considerations and Simulations for Small Integrated Power Devices (February 8, 2011)

Integrated power supplies are now widely used for various laptop, server, and graphics’ cards voltage rails since they require much less space and footprints than previously used solid state power supplies. However a consequence of a smaller footprint is a more complicated cooling design. Even though heat fluxes may only approach 50W/cm2 , limited space and footprint size limit direct convection, radiation, and heatsinking for the chip package so use of heat conduction paths to the primary layer, thermal vias, and FET power layout is critical to meet thermal requirements. This presentation will focus on different cooling techniques and practices of integrated power supply chip packages and thermal issues commonly encountered with such chip packages. The outline of this discussion will include the following; thermal resistance of a power supply chip package system, nonuniform FET power distribution, conduction paths to the pcb primary layer, thermal vias (common shapes and sizes) and heat conduction to remaining pcb copper layers, and multiphase package cooling.

 

  

Ernie is currently working as the thermal/mechanical design engineer at Volterra Semiconductors in Fremont, CA Volterra Semiconductors supplies integrated power supply chip packages to most laptop, server, graphics, and desktop manufacturers including HP, Lenovo, Alcatel, IBM, AMD, and Nvidia. Prior to working at Volterra Semiconductors, Ernie was a thermal design engineer at Nokia, Mountain View, CA and Applied Thermal Technologies in Santa Clara, CA.
At Nokia he led the 1U-3U firewall server thermal designs and participated in the mobile handset thermal design. At Applied Thermal technologies he was a consultant for several companies in the Silicon Valley including Cisco, Apple, HP, Force 10 Networks, Nvidia, BioRad, Rambus, Tyco Electronics, ATI, and Sun Microsystems.

He received his Bachelor of Science Degree in Mechanical Engineering with a specialty in Thermal/Fluid science from Washington State University in 1989, his Master of Science Degree in Aeronautical/Aeroacoustical Engineering from George Washington University and NASA Langley Research Center in 1992, and his Doctor of Philosophy Degree in Mechanical Engineering with a specialization in Fluid Mechanics Measurements in 1996 from University of Utah. He enjoys windsurfing and being outdoors and has been teaching part time for San Jose State University’s Mechanical and Aerospace Engineering Department for eleven years.

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Bernie Siegal, CEO, Thermal Engineering Associates, Inc.
  

Thermal Test Chips & Thermal Test Vehicles – Tools for Thermal Management Design (January 11, 2011)

Increasing device complexity, greater power densities, ever changing packages, and shorter time-to-market deadlines have combined to make thermal characterization efforts more frenzied than ever. A thermal test chip was designed to assist the thermal engineer in answering critical thermal packaging or material questions. It has a standard heat source with integrated temperature sensors in a format that can handle both wire bond and bump chip configurations in a scalable array size. This allows a single wafer to supply various array sizes to meet changing requirements. This presentation will describe the key elements of a thermal test chip that meets these requirements in the simplest manner possible and the packaging of the chip into test vehicle for practical applications.

 

  

Bernie Siegal's first involvement in semiconductor thermal matters came in 1966 while working at Hewlett-Packard Associates (HPA), the HP microwave semiconductor group. He and an associate developed a automated system for making thermal resistance measurements on microwave diodes and authored the feature article describing the method that appeared in the October 1967 issue of the HP Journal. From that beginning to today, Bernie has been an active participant in the semiconductor thermal measurement, modeling and management field.

In 1974, Bernie founded SAGE Enterprises, Inc. and offered test equipment for measurement of semiconductor device thermal resistance. The thermal testing techniques Bernie developed eventually became incorporated into many of the industry (SEMI and EIA/JEDEC) and US military measurement (Mil Std 750) standards. Bernie was co-founder and primary force behind the start of SEMI-THERM. He has authored over 40 technical papers, presented seminars to world-wide audiences, and conducted several short courses for the Univ. of California,Berkeley, extension program. He founded THERMAL ENGINEERING ASSOCIATES, INC. (TEA) in 1997 to maintain his involvement in the field. Bernie holds M.B.A. (Santa ClaraUniversity), M.S.E.E. (San JoseStateUniversity), and B.E.E. (CornellUniversity) degrees. He was elected a Life Fellow of the IEEE and received the IEEE Significant Contributor Award for his work in the semiconductor thermal field. He currently serves on the Executive Committee for the IEEE CPMT Silicon Valley Chapter and is Chairman of the Steering Committee for SEMI-THERM (Semiconductor Thermal Measurement, Modeling and Management) symposium. He is continues to be an active participant in the JEDEC JC15 activities.

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Prof. Ali Shakouri, University of California, Santa Cruz
  

Nanoscale Thermo Electric Energy Conversion Devices and Measurements (November 9, 2010)

Energy consumption in our society is increasing rapidly. A significant fraction of the energy is lost in the form of heat. In this talk we introduce thermoelectric devices that allow direct conversion of heat into electricity. Novel metal-semiconductor nanocomposites are developed where the heat and charge transport are modified at the atomic level. Theory and experiment are compared for the case of embeddded nanoparticles in a semiconductor matrix as well as in multilayer films. Potential to reach energy conversion efficiencies exceeding 20% and the trade-off between material cost and system efficiency are discussed. We also describe how similar principles can be used to make micro refrigerators on a chip with cooling power densities exceeding 500 watts per centimeter square. Finally, we describe some recent advances in nanoscale thermal characterization and modeling. Thermoreflectance imaging is used to measure the transient temperature distribution in power transistors, interconnect vias, solar cells and LEDs with down to 800ps time and submicron spatial resolution. In analogy with image blurring, a new technique is developed to estimate the temperature profile in integrated circuit chips with calculation speeds hundreds of times faster than the standard finite element methods. Comparison with the state-of-the-art architecture level thermal simulators such as HotSpot and Sesctherm is given.

 

  

Ali Shakouri is Professor of Electrical Engineering at University of California Santa Cruz. He received his Ph.D. from California Institute of Technology in 1995. His current research is on nanoscale heat and current transport in semiconductor devices, high resolution thermal imaging, micro refrigerators on a chip and waste heat recovery. He is also working on a new sustainability curriculum in collaboration with colleagues in engineering and social sciences.

He has initiated an international summer school on renewable energies sources in practice. He is the director of the Thermionic Energy Conversion center, a multi-university collaboration aiming to improve direct thermal to electric energy conversion technologies. He received the Packard Fellowship in Science and Engineering in 1999, the NSF Career award in 2000 and UCSC School of Engineering FIRST Professor Award in 2004.

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Bernie Siegal, CEO, Thermal Engineering Associates, Inc.
  

Solar Photovoltaic Cells from a Thermal Perspective (October 12, 2010)

One of the key power generation technologies in the current "green" revolution is the solar photovoltaic cell (SPVC). This unit directly converts solar energy into useful amounts of electrical energy in an increasingly economically-efficient manner. But the SPVC is not a new device - in semiconductor device terms, it is just a diode, and has been around for many decades. The newness of the SPVC lies in the increased energy conversion efficiencies and the ability of industry to find ways to lower the manufacturing and implementation costs while improving the performance and reliability. A key element in the performance and reliability improvements has centered on better control of the cell's junction temperature (TJ). This presentation will cover different types of SPVCs, SPVC performance limiters, incident power considerations, and a thermal measurement approach.

 

  

Bernie Siegal's first involvement in semiconductor thermal matters came in 1966 while working at Hewlett-Packard Associates (HPA), the HP microwave semiconductor group. He and an associate developed a automated system for making thermal resistance measurements on microwave diodes and authored the feature article describing the method that appeared in the October 1967 issue of the HP Journal. From that beginning to today, Bernie has been an active participant in the semiconductor thermal measurement, modeling and management field.

In 1974, Bernie founded SAGE Enterprises, Inc. and offered test equipment for measurement of semiconductor device thermal resistance. The thermal testing techniques Bernie developed eventually became incorporated into many of the industry (SEMI and EIA/JEDEC) and US military measurement (Mil Std 750) standards. Bernie was co-founder and primary force behind the start of SEMI-THERM. He has authored over 40 technical papers, presented seminars to world-wide audiences, and conducted several short courses for the Univ. of California,Berkeley, extension program. He founded THERMAL ENGINEERING ASSOCIATES, INC. (TEA) in 1997 to maintain his involvement in the field. Bernie holds M.B.A. (Santa ClaraUniversity), M.S.E.E. (San JoseStateUniversity), and B.E.E. (CornellUniversity) degrees. He was elected a Life Fellow of the IEEE and received the IEEE Significant Contributor Award for his work in the semiconductor thermal field. He currently serves on the Executive Committee for the IEEE CPMT Silicon Valley Chapter and is Chairman of the Steering Committee for SEMI-THERM (Semiconductor Thermal Measurement, Modeling and Management) symposium. He is continues to be an active participant in the JEDEC JC15 activities.

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Bob Seese, Chief Data Center Architect, Advance Data Center
  

Operational Considerations in Managing Complex Thermal Environments (September 14, 2010)

Air management is now the single most critical environmental concern of data center operators. Providing robust solutions that reduce this burden while addressing the growing global concerns for energy efficiency are the challenges facing vendors at every level of the facility design as well as the entire IT stack. Constant equipment churn, increasing rack heat densities, technology refreshes and planning for changes in a manner that provides for smooth uninterrupted operations of the environment are only some of the daily challenges faced by data center operators. A few ideas for improvements to existing infrastructure products that will help increase the effective management of these environments will be presented. Vendors that address these concerns will be able to clearly differentiate their products from competitors.

  

With more than 20 years of global data center design, project engineering, and project management experience, Bob Seese has worked extensively in the mission-critical facility, facility management, and construction industries. Formerly the Chief Data Center Architect with EDS and the Director of Data Center Development with Equinix, he has managed numerous data center projects and has helped design many of the world's cutting edge facilities. While with Netscape and AOL, Bob helped design and build more than 300,000 square feet of data center space throughout the U.S. More recently, as a data center consultant, he has provided design assistance and training as well as end-to-end project support for engineers and end-users worldwide.


He has authored and co-authored numerous technical articles and presented to groups and organizations globally on issues related to energy efficiency in mission-critical environments, and on specific data center design concepts. He has completed in excess of 800 data center audits worldwide and has amassed a vast library of the "best and worst practices" in the design and operation of those facilities.

As a recognized leader in energy conservation, he participated in the San Jose Green Building Task Force and was later appointed by the mayor to a blue ribbon task force charged with evangelizing and implementing the city's first green building initiative. He actively participated in the Rocky Mountain Institute's Integrated Design Charrette, which resulted in the publication of the often quoted "Design Recommendations for High-Performance Data Centers". And, as a founding member of the Critical Facility Roundtable, Bob has continued to promote energy efficient design particularly in mission-critical environments.

Bob holds a Master's degree in Mechanical Engineering and a PhD in Educational Management, as well as Bachelor's degrees in Motion Pictures and Television and Liberal Arts.

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Thomas S. Tarter, Package Science Services LLC
  

Stacked Chip Technology Powers Up (August 10, 2010)

Chip stacking has been a part of integrated circuit technology for longer than most realize. One area where great difficulty in removing heat is found is in the stacking of chips in a single package. As 3D packaging was proven as a reliable system with potential cost savings, more designs were developed beyond the single-chip stack to system-in-package designs. Thermal management considerations for these packages become complex, due to the chips in the middle of the stack having no direct path for heat flow to the ambient. Thermal problems due to high-power chips anywhere in the stack and the inability to dictate the ‘order’ of the stacked chips create challenges in cooling. Recently, through-silicon via interconnection (TSV) has been developed to interconnect stacked chips without the constraints of wire bonding. The TSV approach makes the 3D stack even more compact, but exacerbates thermal management problems. Currently there are no standard approaches for cooling stacked chips due to the multiple types and approaches being taken. This talk will focus on removing heat from TSV stacked chip packages and will discuss methods and techniques for thermal management of stacked-chip packaging.

  

Thomas S. Tarter is an expert on thermal management, thermal and electrical characterization, and design of microelectronic and optoelectronic packaging structures. He spent 17 years at AMD in package characterization and was a Senior Member of the Technical Staff. Subsequently he was Director of BGA Package Engineering and Design at Advanced Interconnect Technology, and Principal Engineer for thermal management, temperature control and package development at NeoPhotonics Corporation, Inc.

In 2009, Tom started Package Science Services LLC, to serve the high-tech community with electronic packaging expertise in design, analysis, and characterization (electrical, thermal, reliability) and support all phases of IC, solar cell, LED and other chip packaging from concept to hand off to mass manufacturing. Tom has published 30 papers, holds 5 patents, and has presented numerous short courses and lectures. He chaired the JEDEC JC15.1 task group on thermal standards for five years, was general chair of SEMI-THERM, Technical Chair for five years, and serves on the SEMI-THERM executive committee to date. Tom is a senior member of IEEE and was chair of the IEEE Santa Clara Valley Chapter of CPMT for two years. Society affiliations include, IEEE, LEOS, Santa Clara Valley Nanotechnology Council, MEPTEC, IMAPS, and SPIE.

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David Copeland, Thermal Engineer, Oracle's Microelectronics Group - Packaging Technology Department
  

Leakage Effects, Energy Minimization and Performance Maximization (July 13, 2010)

Leakage has become an increasing fraction of processor power with each technology node. As leakage is strongly temperature dependent, processor power dissipation can be reduced by increasing fan/blower power to provide air at a higher volume flow rate and/or pressure drop. A global optimum can be achieved as a function of the leakage and heatsink characteristics.

Processor frequency is strongly dependent on temperature and voltage. The voltage dependence is approximately proportional, while temperature dependence has reduced with each technology node. In the near future, the temperature dependence may near zero and possibly even result in reduced frequency at reduced temperature. Even in such a case, if the processor voltage is increased at reduced temperature, which is in turn achieved by increased fan/blower power, energy can be minimized and performance maximized at lower temperatures. A parametric study encompassing past, present and future ranges of leakage and temperature effects is presented.

 

  

David Copeland is a Thermal Engineer working in the Packaging Technology department of Oracle's Microelectronics Group, developing packaging and cooling technology for UltraSPARC processors and the systems which use them. Areas of development include thermal interfaces, heat spreading materials, single-phase and phase-change liquid cooling, and data center cooling. He received his BS from Massachusetts Institute of Technology, MS from Stanford University and DrEng from Tokyo Institute of Technology, all in Mechanical Engineering.

Before coming to Sun in 2005, he worked in packaging and cooling at IBM, Hitachi and Fujitsu, and in heatsink development and design at Intricast, Sumitomo and Showa Aluminum. David belongs to ASME, IEEE and IMAPS, and is a frequent participant at conferences on electronics cooling.

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Marlin Vogel, Director of Business Development, Electronic Cooling Solutions, Inc
  

Tower & Low Profile Heat Pipe Heat Sink and Self-Contained Pumped Coolant Systems (June 8, 2010)

In order to meet the next generation CPU thermal requirements with a phase change heat sink, three heat sink technologies and their associated prototypes will be described. Each of the heat sink technologies use internal liquid-to-vapor phase change to efficiently spread the local CPU power to the air-cooled fin structure. The three passive phase change heat sink technologies are: multiple embedded heat pipes; vapor chamber base, and a hybrid vapor chamber / multiple tower heat pipes. Maintaining the same CPU module spatial envelope and air flow requirements for follow-on CPU designs in air-cooled servers will require on board, self contained, pumped coolant solutions that incorporate micro-channel cold plates with relatively low coolant pressure loss due to the current practical performance limitations of the passive phase change heat sink evaporator and condenser. Three pumped coolant technologies and their associated prototypes that met the increased thermal performance requirements will be described.

Typically in the past, if two heat sink technologies met the thermal performance requirements along with meeting the reliability performance requirements, the least expensive technology would be utilized. In the future, heat sink thermal performance specifications will consider including the impact of energy cost savings attained through reduced server air flow rate requirements if utilizing a superior heat sink technology warrants a potential increase in heat sink cost.

  

Marlin Vogel joined Electronic Cooling Solutions as the Director of Business Development in January, 2010. Marlin was a Sr. Staff level engineer at Sun Microsystems, where he conducted research, development, and productizing thermal technologies for CPU applications for 18 years, beginning in 1991. He lead the CPU module and system thermal development efforts for the high end sparc servers since 2002. Prior to joining Sun Microsystems Marlin was a member of the General Dynamics Thermodynamics Analysis group for 7 years, serving as co-leader of the thermal design effort for a Navy stealth jet aircraft engine exhaust.

Marlin obtained his Mechanical Engineering degree in 1979 and his M.S. degree in 1984 from the University of Wisconsin – Milwaukee and has authored several conference and journal papers on electronic cooling, and has been awarded 11 patents on electronic cooling inventions.

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Howard Harrison, President of Distributed Thermal Systems (DTS) Ltd.
  

Using Flow Optimizers to Save Cooing Fan Power (May 11, 2010)

The green data center initiative has increased everyone's awareness of power consumption. Cooling fans, although small relative to CRAC units and other large components, typically consume 5 to 15 % of server power. The number is even higher for series fan configurations, as performance has traditionally suffered due to the swirl between the fans. This talk will focus on the use of DTS flow optimizers to increase the efficiency of the series configuration beyond that of the underlying fans, thereby enhancing performance beyond the two fan theoretical limit. In most cases this will allow fan power to be reduced by ~20% while still achieving the required operating point. The latent thermal headroom may be used to accommodate future upgrades and increases in component density, without changing the fans.

An introduction to flow optimizers will be followed by a review of performance and efficiency results from a variety of fan sizes, designs and manufacturers. Then two brief case studies will highlight actual power savings and latent thermal headroom results for 1U and large format servers. Additional examples will include blower replacement and extreme static pressure configurations. Finally, the presentation of a general design methodology for implementing flow optimizers will be followed by an open discussion and Q&A.

  

Howard Harrison is the founder and President of Distributed Thermal Systems (DTS) Ltd., which has developed the flow optimizer technology in conjunction with the University of Waterloo. Prior to that he spent 14 years in the systems industry with Hewlett Packard and Digital Equipment Corporation. Howard earned a BSc. in Electrical Engineering from Queen's University as well as an MBA from the University of Toronto.

He holds several patents and patents pending, and has co-authored a variety of papers on the subject matter, most recently at SEMITHERM 2010 in San Jose.

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Ihab Andre Ali, Vice President of Thermal Products, Pipeline Micro, Inc
  

Challenges of Thermal Management and Design of Compact 3-D Microsystems - An Integrated System-Level Approach with Focus on Discrete Technologies (April 13, 2010)

The talk provides an overall review of thermal design performance limitations and thermal management techniques covering 3-D Microsystems with focus on mobile and handheld products. Thermal challenges are discussed including a key thermal design parameter concerning outer skin temperature limits based on natural convection and radiation with the ambient. Passive conduction techniques to increase the internal thermal performance of boards, substrates and IC packages are discussed. The talk provides an overview on internal IC's thermal performance enhancements utilizing liquid cooling. The discussion walks through a numerical example introducing an efficient microchannel pumped liquid cooled system for compact electronic form factors. The performance of the liquid cooled system is discussed at length and compared to conventional heat pipe based thermal architecture. Tradeoffs of various system related parameters are discussed in details. The talk while showing the benefit of liquid cooling in general, it focuses on the importance of taking an integrated system approach for thermal design of systems. The role of liquid cooling of increasing systems thermal performance can be significantly enhanced when factoring into the design and optimization the above system parameters.

 

  

Andre is currently vice president of thermal products at Pipeline Micro, Inc., an advanced electronic cooling and micro fabrication startup. Andre is a founder of Rola Technologies, a technical, market and product strategy consulting company in electronics thermal design and energy efficiency markets. He is a former chief thermal architect at Apple where he is credited for leading and innovating thermal technologies and design architectures for Apple's MacBook, MacBook Pro, MacBook Air, iMac, iPhone and other platforms. He is a former thermal technology engineer at Intel's mobile product group. His interests and research focus are in electronics thermal management and control, energy efficiency, renewable energy and environmental impact.


Andre is an inventor of over 20 patents and applications and publisher of numerous papers in the field of thermal management and heat transfer. He also served as keynote speaker, panelist and chair at various conferences and forums worldwide. Andre has a BS in civil engineering from Damascus University and MS in mechanical engineering from WPI.

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Magnus Herrlin, President, ANSIC, Inc.
  

Thermal Design of Data Centers to Safeguard the Electronic Equipment (March 9, 2010)

Electronic equipment manufacturers guarantee the thermal design of their products. They specify the required air intake temperatures to satisfy the cooling requirements. The thermal designer of the data center room ensures that the air drawn into the equipment meets or exceeds the manufacturers' specifications. Both the manufacturers and the data center designer need to understand the well-defined thermal interface between the equipment and the room. This presentation reviews methods and tools for designing and maintaining effective thermal equipment environments.

 

  

Dr. Magnus K. Herrlin is President of ANCIS Incorporated, a San Francisco based consultancy providing thermal and energy solutions for data centers and telecom central offices. Prior to establishing ANCIS, he served ten years as Principal Scientist with Bell Communications Research where he led efforts in optimizing energy and cooling efficiency of equipment rooms. Earlier, he served six years as Visiting Scientist with Lawrence Berkeley Laboratory (LBL).

Recent high-profile activities include:
 >Lead of the development of the Data Center Certified Energy Practitioner (DC-CEP) Program for the Department of Energy (DOE)
 >Provided CFD modeling and analysis of the first U.S. pre-qualified Platinum LEED data center for Advanced Data Centers (ADC)
 >Developed air-management solutions for the next Supercomputer Center at Lawrence Berkeley National Laboratory (LBNL).

Magnus is a Member of ASME and ASHRAE. Magnus holds a Ph.D. and an M.S. in Mechanical Engineering and is a Certified Energy Manager (CEM) by the Association of Energy Engineers.

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Tom Tarter, Proprietor and Principal Engineer, Package Science Services
  

Design of High Density Packaging: Tools and Knowledge (February 9, 2010)

Packaging of complex silicon devices requires a deep knowledge of many aspects of high-technology engineering disciplines. As an example, packaging a high lead-count chip requires knowledge of electrical, thermal, mechanical, chemical and manufacturing engineering. These disciplines must be known and must be used in the conceptualization, design and implementation of any package design. Complex systems many times require more than one die in the package. These chips can be stacked or arrayed onto a substrate to increase functionality and reduce size and cost, driving the complexity of the package beyond the capability of simple drawings and 2D design tools.

 

  

Mr. Tom Tarter is the proprietor and principal engineer of Package Science Services. He was a working professional in the area of thermal management and electrical characterization of packaging structures. He spent over 16 years at Advanced Micro Devices (Sunnyvale, CA) in package characterization and left as a Senior Member of the Technical Staff. After a short time as Director of BGA Package Engineering and Design at Advanced Interconnect Technology (Pleasanton, CA) he was responsible for thermal management, temperature control, and package development at Neo Photonics Corporation (San Jose / Fremont, CA). His knowledge of microelectronic and optical packaging spans this career and he is a noted expert on thermal and electrical characterization of packages, both in the microelectronic and optoelectronic regimes.


Tom has authored or co-authored over 20 published papers and numerous short courses and lectures on thermal and electrical phenomenon in microelectronic packaging and most recently in optoelectronic packaging. He has presented short courses and technical papers at conferences and technical meetings around the world. An invited lecturer and author, he has also lectured at graduate level short courses on micro- and opto-electronic packaging at UC Santa Cruz extension and San Jose State University.

Tom chaired the JEDEC JC15.1 task group on thermal standards for five years, and was general chair of the JC15 thermal and electrical characterization standards group for two years. He was general chair of the semiconductor heat transfer conference SemiTherm XIII, and serves on the executive committee of SemiTherm to date. He is also vice-technical chair for SEMI-International Electronics Manufacturing Technology Conference and is the technical program chair for Wescon 2003. Tom was the chapter chair for the IEEE Silicon Valley Chapter of CPMT. He has worked with the IEEE/CPMT for several years and has an excellent track record of engineering community service. Tom is also a member of IEEE and of the local CPMT and LEOS chapters.

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Guy Wagner, Thermal Consulting Engineer, Electronic Cooling Solutions Inc.,
  

Designing with Thermoelectric Coolers and Generators (January 12, 2010)

With increasing interest in solid-state cooling and power generation, the use of Thermoelectric Coolers (TECs) and Thermoelectric Generators (TEGs) is on the upswing. This presentation will cover the advantages and limitations of designing with TEC and TEGs. Techniques will be demonstrated showing how to efficiently use iterative techniques within a spreadsheet to effectively run a transient thermal analysis involving a TEC. Also demonstrated will be the use of the TEC SmartPart model within Flotherm to analyze the performance of a system using a TEC.

 

  

Mr. Wagner has over 35 years experience in the electronics industry. His experience includes: IC and system cooling and packaging technology, disk drive design, computer system design, and design of telephone switching systems. Mr. Wagner, an expert in cooling of electronics systems and IC packages, has authored 16 papers and talks at international conferences on this subject and has 26 patents. He is currently a consultant and the owner of RM laboratories. As a consultant he has provided thermal management support to a number of Electronic Cooling Solutions customers as well as to Hewlett Packard, Dell Computers and Vitesse Semiconductors.


Guy Wagner was previously the Director of Engineering for Cornice Reference Designs where he was responsible for the mechanical design of very small form factor (1 inch) hard drive products as well as the world’s smallest MP3 player with a hard drive.

Prior to joining Cornice, he held the position of Chief Scientist for the HP/Agilent Technologies PolarLogic Business unit. Other positions that he held at HP included: Technical Contributor within the HP Work Station Division where he was responsible for the thermal design and management of all HP workstation products and Member of the Technical Staff in Fort Collins where he developed packaging, thermal solutions, and assembly processes for the world’s first 32 bit microprocessor and the first Pin Grid Array and BGA packages.

Prior to joining HP Mr. Wagner held a position as a Member of the Technical Staff at AT&T Bell Laboratories where he was a lead engineer and provided thermal and mechanical design expertise to teams working on telephone switching equipment.

Mr. Wagner received his MS in Mechanical Engineering from Iowa State University.

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Bernie Siegal, CEO, Thermal Engineering Associates, Inc.
  

HiPwr LED Thermal Characterization – Methods and Issues (December 8, 2009)

The lack of industry standards for LED thermal measurements has given rise to confusion about thermal parameters and their applicability to application environments. While the basics of junction temperature measurements are applicable to HiPwr LEDs, defining the thermal measurement environment and test conditions in a manner consistent with application requirements are subject to much discussion. This presentation will discuss the methods and issues relative to thermal measurements and provide a industry status report on thermal issues.

 

  

Bernie Siegal's first involvement in semiconductor thermal matters came in 1966 while working at Hewlett-Packard Associates (HPA), the HP microwave semiconductor group. He and an associate developed a automated system for making thermal resistance measurements on microwave diodes and authored the feature article describing the method that appeared in the October 1967 issue of the HP Journal. From that beginning to today, Bernie has been an active participant in the semiconductor thermal measurement, modeling and management field.

In 1974, Bernie founded SAGE Enterprises, Inc. and offered test equipment for measurement of semiconductor device thermal resistance. The thermal testing techniques Bernie developed eventually became incorporated into many of the industry (SEMI and EIA/JEDEC) and US military measurement (Mil Std 750) standards. Bernie was co-founder and primary force behind the start of SEMI-THERM. He has authored over 40 technical papers, presented seminars to world-wide audiences, and conducted several short courses for the Univ. of California,Berkeley, extension program. He founded THERMAL ENGINEERING ASSOCIATES, INC. (TEA) in 1997 to maintain his involvement in the field. Bernie holds M.B.A. (Santa ClaraUniversity), M.S.E.E. (San JoseStateUniversity), and B.E.E. (CornellUniversity) degrees. He was elected a Life Fellow of the IEEE and received the IEEE Significant Contributor Award for his work in the semiconductor thermal field. He currently serves on the Executive Committee for the IEEE CPMT Silicon Valley Chapter and is Chairman of the Steering Committee for SEMI-THERM (Semiconductor Thermal Measurement, Modeling and Management) symposium. He is continues to be an active participant in the JEDEC JC15 activities.

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Arun P. Raghupathy, Thermal Consulting Engineer, Electronic Cooling Solutions Inc.
  

Boundary-Condition-Independent (BCI) Compact Thermal Models (CTM) for CFD-based Thermal Analysis of Optical Transceivers (November 10, 2009)

A Compact Thermal Model is generated for a multi-heat source optical transceiver called Small Form-factor Pluggable package (SFP). When used in practical applications, the CTM is shown to be capable of predicting results with a maximum relative error of 7% with respect to the detailed model. In addition to presenting the methods, results and benefits of this study, the presentation will also outline goals for extension of this work to other types of optical transceivers.

 

  

Dr. Raghupathy has been with the company for three years. He has extensively worked and published in the areas of thermal management of electronics and reduced-order model development. He holds a doctoral degree in Mechanical Engineering from the University of Cincinnati, OH. He is also an active member of many technical organizations such as IEEE, ASME, AIAA and ASEI.

 

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George A Meyer IV, COO/CTO, Celsia Technologies
  

Understanding heat pipe and vapor chamber performance for design and modeling of thermal solutions (October 13, 2009)

Vapor chamber and heat pipe performance is often misunderstood which results is errors when trying to design thermal solutions using these products. The most common error is to apply an effective thermal conductivity number to these. By applying a thermal conductivity number it is inferring that the device has a linear resistance or delta-t. This is not the case.

This presentation will cover in detail the actual performance of these devices and how to use these numbers in designing thermal solutions.

 

  

Mr. Meyer is a seasoned industry veteran with over three decades experience in electronics thermal management. He has been with Celsia since December 2005, first as VP Sales and Marketing for the Americas and Europe regions and then as COO and CTO. In these roles, Mr. Meyer has been instrumental in establishing Asian operations, developing new technologies, key customer relationships, managing the product portfolio, and growing sales into the computer, telecommunications, LED lighting, medical, and military markets.

Prior to Celsia, he held various positions with Thermacore International (a leading supplier of thermal management solutions) including chairman and general manager of ThermacoreTaiwan and Korea, as well as vice president, worldwide sales and marketing. During his tenure, Meyer was credited with establishing the company’s Asian design and manufacturing facilities, developing patentable product designs, and growing relationships with leading technology companies such as Intel, Hewlett-Packard, Apple, Sun Microsystems and Silicon Graphics. He graduated from PennStateUniversity with a degree in Communications and holds an International Business Certificate from Franklin and MarshallCollege. Mr. Meyer is also a certified 6 Sigma Black Belt and holds 94 domestic and international patents/patents pending in the field of electronics thermal management.

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Bernie Siegal, CEO, Thermal Engineering Associates, Inc.
  

IC Thermal Measurements – According to JEDEC (September 8, 2009)

A gating item in the development of higher performance electronic systems is thermal management of integrated circuit (IC) power dissipation. Knowledge of the IC thermal performance is essential for developing cost-effective thermal management solutions. This presentation is designed for device, packaging and system design professionals who want an introduction to the "art" of integrated circuit thermal measurements in accordance with the JEDEC-standards. Details of junction temperature measurements and thermal test environment will be covered and reference sources will be provided.

 

  

Bernie Siegal's first involvement in semiconductor thermal matters came in 1966 while working at Hewlett-Packard Associates (HPA), the HP microwave semiconductor group. He and an associate developed a automated system for making thermal resistance measurements on microwave diodes and authored the feature article describing the method that appeared in the October 1967 issue of the HP Journal. From that beginning to today, Bernie has been an active participant in the semiconductor thermal measurement, modeling and management field.

In 1974, Bernie founded SAGE Enterprises, Inc. and offered test equipment for measurement of semiconductor device thermal resistance. The thermal testing techniques Bernie developed eventually became incorporated into many of the industry (SEMI and EIA/JEDEC) and US military measurement (Mil Std 750) standards. Bernie was co-founder and primary force behind the start of SEMI-THERM. He has authored over 40 technical papers, presented seminars to world-wide audiences, and conducted several short courses for the Univ. of California,Berkeley, extension program. He founded THERMAL ENGINEERING ASSOCIATES, INC. (TEA) in 1997 to maintain his involvement in the field. Bernie holds M.B.A. (Santa ClaraUnivers<.S.E.E. (San JoseStateUniversity), and B.E.E. (CornellUniversity) degrees. He was elected a Life Fellow of the IEEE and received the IEEE Significant Contributor Award for his work in the semiconductor thermal field. He currently serves on the Executive Committee for the IEEE CPMT Silicon Valley Chapter and is Chairman of the Steering Committee for SEMI-THERM (Semiconductor Thermal Measurement, Modeling and Management) symposium. He is continues to be an active participant in the JEDEC JC15 activities.

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